#include "spim.h"
#include "peripherals.h"
#include "types.h"

static volatile u8 rxd[SPI_X_BUFFER_SIZE];
static volatile u8 txd[SPI_MAX_BUFFER_SIZE];

enum spim_register {
	TASKS_START = 0x10,
	TASKS_STOP = 0x14,
	TASKS_SUSPEND = 0x1c,
	TASKS_RESUME = 0x20,
	EVENTS_STOPPED = 0x104,
	EVENTS_ENDRX = 0x110,
	EVENTS_END = 0x118,
	EVENTS_ENDTX = 0x120,
	EVENTS_STARTED = 0x14c,
	SHORTS = 0x200,
	INTENSET = 0x304,
	INTENCLR = 0x308,
	ENABLE = 0x500,
	PSEL_SCK = 0x508,
	PSEL_MOSI = 0x50c,
	PSEL_MISO = 0x510,
	FREQUENCY = 0x524,
	RXD_PTR = 0x534,
	RXD_MAXCNT = 0x538,
	RXD_AMOUNT = 0x53c,
	RXD_LIST = 0x540,
	TXD_PTR = 0x544,
	TXD_MAXCNT = 0x548,
	TXD_AMOUNT = 0x54c,
	TXD_LIST = 0x550,
	CONFIG = 0x554,
	ORC = 0x5c0,
};

static u8 spim_write_reg(u8 spi_index, enum spim_register reg, u32 value) {
	switch (spi_index) {
		case 0:
			WRITE_REGISTER(SPI0, reg, value);
			return 1;

		case 1:
			WRITE_REGISTER(SPI1, reg, value);
			return 1;

		case 2:
			WRITE_REGISTER(SPI2, reg, value);
			return 1;

		default:
			return 0;
	}
}

static u32 spim_read_reg(u8 spi_index, enum spim_register reg) {
	switch (spi_index) {
		case 0:
			return READ_REGISTER(SPI0, reg);

		case 1:
			return READ_REGISTER(SPI1, reg);

		case 2:
			return READ_REGISTER(SPI2, reg);
	}
}

u8 spim_setup(u8 spi_index, struct spim_setup_info setup_info) {
	if (spi_index > 2) {
		return 0;
	}

	/* Write to register blah blah blah*/
}

void spim_send(u8 spi_index, u8 *write_buffer, u8 *read_buffer) {

}

void spim_stop(u8 spi_index) {

}